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[ak7742] ms1024-e-00_pb 2008/11 - 1 - the ak7742 is a highly integrated audio digital processor, including two stereo 24bit dac?s and one stereo adc with input selector. the stereo dac and adc feature high perform ance, archiving 106db and 96db dynamic range respectively, 8k hz to 96khz sampling rate ar e supported. the audio dsp has 1536step/fs parallel processing power , and 74k-bit delay memory allo ws surround processing, acoustic effect and parametric equalizers. as the ak7742 is a ram based dsp, it is programmable for user requirements. the ak7742 is available in a space saving small 48pin lqfp package. dsp: - word length: 24bit (data ram 24bit floating point) - instruction cycle: 13.6 ns (1536step/fs fs=48khz; 9216step/fs fs=8khz) - multiplier 20 x 16 36bit (double precision available) - divider 20 / 20 20bit - alu: 40bit arithmetic operation (overflow marg in 4bit) 24bit floating point arithmetic and logic operation - program ram: 1536 x 36bit - coefficient ram: 1536 x 16bit - data ram: 1536 x 24-bit (24bit floating point) - delay ram: 74kbit (3072 x 24bit) - sampling frequency: 8khz ~ 96khz - master / slave operation - serial signal input port (4ch) msb justifie d 24bit / lsb justified 24 / 20 / 16bit and i 2 s - serial signal output port (6ch) msb justif ied 24bit / lsb justified 24 / 16bit and i 2 s adc: 2ch (stereo) - 24bit 64 x over-sampling delta sigma (fs=8khz~48khz) - dr, s/n: 96db (fs=48khz, fully differential input) - s/(n+d): 84db (fs=48khz) - differential, single-end inputs - digital hpf (fc=1hz) - 3:1 analog input selector - digital volume (24db~-103db, 0.5db step, mute) dac: 4ch (two stereo pairs) - 24bit 128 x over-sampling advanced multi-bit (fs=8khz~96khz) - dr, s/n: 106db - s/(n+d): 92db - differential output - digital volume (12db~-115db, 0.5db step, mute) dsp through mode i 2 c bus interface for micro-controller power supply: +3.3v 0.3v, internal regulator for 1.8v operating temperature range: -20 c~70 c (ak7742eq), -20 c~85 c (AK7742EN) package: 48pin lqfp, 0.5mm pitch (ak7742eq) 48pin qfn, 0.4mm pitch (AK7742EN) general description features 24bit 2ch adc + 24bit 4ch dac with audio dsp ak7742
[ak7742] ms1024-e-00_pb 2008/11 - 2 - block diagram figure 1. block diagram pull down hi-z clko/sdout3 2 3 dvdd vss1 clkoe open drain scl cad0 cad1 so/rdy/gpo/sdout2 sda i2csel micif sdin1 / jx1 jx1e sdin2 / jx0 jx0e jx1 jx0 din2 din1 din3 dout3 dout4 ds out1e sdout1 adc xto xti clkgen & cont lflt iresetn 3 ckm[2:0] test1 bick lrck 2 1 0 ain1lp,ain1ln ain1rp,ain1rn 4 2 2 ain2l,ain2r ain3l,ain3r sdoutad dac2 aout2lp aout2ln aout2rp aout2rn dac1 aout1lp aout1ln aout1rp aout1rn dout1 sdinda2 sdinda1 ref vcom avdrv dout2 so rdy 1 0 2 0 1 seldo1 seldo4[1:0] seldo5[1:0] 3 asel[1:0] seldo2[1:0] 0 1 dout5 3 gpo seldo3 out2en 0 1 2 3 0 1 2 3 dvol dvol dvol avdd 3 vss2 2
[ak7742] ms1024-e-00_pb 2008/11 - 3 - cp0, cp1 cram 1536w x 16-bit dp0, dp1 dram 1536w x 24-bit mpx16 mpx20 ofreg 64w x 13-bit x y multiply 16 x 20 36-bit micon i/f control pram 1536w x 36-bit dec pc stack : 5level(max) mul dbus shift a b alu 40-bit overflow margin: 4-bit dr0 3 over flow data generator division 20 20 20 peak detector serial i/f cbus(16-bit) dbus(24-bit) 36-bit 24-bit 40-bit 40-bit 40-bit dlram 3072w x 24-bit ptmp(lifo) 6 x 24-bit dlp0, dlp1 2 x 24,20,16-bit 2 x 24,20,16-bit din1 din2 dout4 (dac1) 2 x 24,20,16-bit 2 x 24,20,16-bit 40-bit dout5 (dac2) dout1 tmp 8 x 24-bit 2 x 24,20,16-bit 2 x 24,16-bit din3 (adc) dout2 dout3 2 x 24,16-bit 2 x 24,16-bit figure 2. ak7742 dsp block
[ak7742] ms1024-e-00_pb 2008/11 - 4 - ordering guide ak7742eq -20 +70 c 48pin lqfp (0.5mm pitch) AK7742EN -20 +85 c 48pin qfn (0.4mm pitch) akd7742 evaluation board for the ak7742 pin layout ak7742eq a vdd cad1 lrck ( top view ) 48pin lqfp xti lflt xto ain3l a in1ln a in1rp test1 a out2ln vss1 a vdrv sda scl sdin2/jx0 so/rdy/gpo/sdout2 1 12 3 2 5 4 7 6 9 8 10 11 38 37 43 42 41 40 39 47 46 45 44 48 21 20 19 18 17 15 16 23 22 13 14 24 32 30 31 28 29 26 27 35 25 33 34 36 sdout1 cad0 a in1lp a in3r a out1ln a out1lp a out1rn vss1 a vdd sdin1/jx1 ckm[1] ckm[0] ckm[2] vss2 dvdd a out1rp a out2rn clko/sdout3 a out2lp a out2rp vcom a in1rn ain2r ain2l avdd vss1 vss2 iresetn i2csel dvdd input output i/o power pin input output i/o power pin bick
[ak7742] ms1024-e-00_pb 2008/11 - 5 - AK7742EN AK7742EN top view ain3l ain2 r ain2l avdd vss1 lflt test1 1 2 3 4 5 8 dvdd 10 xti 7 11 6 12 9 aout2lp aout2ln aout2rp aout2rn a vdd a vdrv vss1 cad0 sda 36 35 34 33 32 29 27 30 26 31 25 28 cad1 scl so/rdy/gpo/sdout2 lrck vss2 dvdd i2csel iresetn ckm[0] clko/sdout3 bick ckm[1] sdin2/jx0 sdin1/jx1 sdout1 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 a out1ln a out1lp vss1 vcom avdd ain1rn a out1rn a out1rp a in1rp a in1ln a in1lp a in3r ckm [ 2 ] vss2 xto
[ak7742] ms1024-e-00_pb 2008/11 - 6 - no. pin name i/o function classification 1 ain3l i adc lch single-end input 3 pin analog input 2 ain2r i adc rch single-end input 2 pin analog input 3 ain2l i adc lch single-end input 2 pin analog input 4 avdd power supply pin for analog section 3.0v ~ 3.6v analog power supply 5 vss1 analog ground 0v analog power supply 6 lflt o filter connection pin for pll connect c=12nf to vss1. ?l? output during initial reset. analog output 7 test1 i test pin (internal pull-down resistor) connect to vss2 test 8 ckm[2] i clock mode select pin 2 mode select 9 dvdd power supply pin for digital section 3.0v ~ 3.6v digital power supply 10 vss2 digital ground 0v digital power supply 11 xti i master clock input pin when using a crystal oscillator, connect it between this pin and xto. when using external main clock, input to this pin with cmos level. clock 12 xto o crystal oscillator output pin when using a crystal oscillator, connect it between this pin and xti. when not using crystal oscillator, leave open. output during initial reset is not determined. clock 13 sdout1 o dsp serial data output pin ?l? output during initial reset data interface 14 sdin1/jx1 i serial data i nput pin 1 / jx1 data interface 15 sdin2/jx0 i serial data i nput pin 2 / jx0 data interface 16 ckm[1] i clock mode select pin 1 mode select 17 ckm[0] i clock mode select pin 0 mode select 18 iresetn i reset pin (for initialization) reset 19 i2csel i i 2 cbus select pin connect to dvdd microcomputer i/f 20 dvdd power supply pin for digital section 3.0v ~ 3.6v digital power supply 21 vss2 digital ground 0v digital power supply 22 lrck i/o lr channel select clock pin ?l? output during initial reset with master mode. data interface 23 bick i/o serial bit clock pin ?l? output during initial reset with master mode. data interface 24 clko/sdout3 o clock output / dsp serial data output pin ?l? output during initial reset clock 25 so/rdy/gpo/ sdout2 o serial data output pin / data write ready output pin / general purpose output / dsp serial data output pin ?l? output during initial reset microcomputer i/f 26 sda i/o sda i 2 c bus interface microcomputer i/f 27 scl i scl i 2 c bus interface microcomputer i/f 28 cad0 i i 2 c bus address pin 0 microcomputer i/f 29 cad1 i i 2 c bus address pin 1 microcomputer i/f 30 vss1 analog ground 0v analog power supply pin function
[ak7742] ms1024-e-00_pb 2008/11 - 7 - 31 avdrv o avdrv pin connect 1 f to vss1. never to use for external circuit. ?l? output during initial reset analog power supply 32 avdd power supply pin for analog section 3.0v ~ 3.6v analog power supply 33 aout2rn o dac2 rch differential inverted analog output pin ?hi-z? output during initial reset analog output 34 aout2rp o dac2 rch differential non-inverted analog output pin ?hi-z? output during initial reset analog output 35 aout2ln o dac2 lch differential inverted analog output pin ?hi-z? output during initial reset analog output 36 aout2lp o dac2 lch differential non-inverted analog output pin ?hi-z? output during initial reset analog output 37 aout1rn o dac1 rch differential inverted analog output pin ?hi-z? output during initial reset analog output 38 aout1rp o dac1 rch differential non-inverted analog output pin ?hi-z? output during initial reset analog output 39 aout1ln o dac1 lch differential inverted analog output pin ?hi-z? output during initial reset analog output 40 aout1lp o dac1 lch differential non-inverted analog output pin ?hi-z? output during initial reset analog output 41 vss1 analog ground 0v analog power supply 42 vcom o analog common voltage connect 0.1 f and 2.2 f in parallel to vss1. never to use for external circuit. ?l? output during initial reset analog output 43 avdd power supply pin for analog section 3.0v ~ 3.6v analog power supply 44 ain1rn i adc rch differential inverted analog input pin analog input 45 ain1rp i adc rch differential non-inverted analog input pin analog input 46 ain1ln i adc lch differential inverted analog input pin analog input 47 ain1lp i adc lch differential non-inverted analog input pin analog input 48 ain3r i adc rch single-end input 3 pin analog input note: digital input pins are never to be left open. if analog input pins (ain1lp, ain1ln, ain1rp, ain1rn, ain2l, ain2r, ain3l, ain3r) are not used, leave them open.
[ak7742] ms1024-e-00_pb 2008/11 - 8 - (vss1=vss2=0v: note 1 ) item symbol min max unit power supply voltage (avdd= dvdd) analog digital avdd dvdd -0.3 -0.3 4.3 4.3 v v input current (except for power supply pin) iin - 10 ma analog input voltage ( note 2 ) ain1lp, ainl1n, ain1rp, ainr1n, ain2l, ain2r, ain3l, ain3r vina -0.3 (avdd+0.3) or 4.3 v digital input voltage ( note 3 ) vind -0.3 (dvdd+0.3) or 4.3 v ak7742eq ta -20 70 oc operating ambient temperature AK7742EN ta -20 70 oc storage temperature tstg -65 150 oc note 1. all indicated voltages are with respect to ground. vss1 and vss2 must be the same voltage. note 2. the maximum value of analog input voltage is smaller value between (avdd+0.3)v and 4.3v. note 3. the maximum value of digital input voltage is smaller value between (dvdd+ 0.3)v and 4.3v. warning: operating at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these critical conditions. (vss1=vss2=0v: note 1 ) item symbol min typ max unit power supply voltage analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 3.6 v v warning: akemd assumes no responsibility for the usage beyond the conditions in the datasheet. note) do not turn off the power of the ak7742 during the power supplies of surrounding devices are turned on. dvdd must not exceed the pull-up of sda and scl of i 2 c bus. (the diode exists for dvdd in the sda and scl pins.) absolute maxmum rating recommended operating conditions
[ak7742] ms1024-e-00_pb 2008/11 - 9 - adc characteristics (ta=25oc; avdd=dvdd=3.3v; bick=64fs; signal freque ncy 1khz; measurement bandwidth=20hz~20khz, fs=48khz, adc differential input, ckm mode 0 (ckm[2:0]=000), unless otherwise specified) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) (-1dbfs) ( note 4 ) 76 84 db dynamic range (a-weighted) ( note 4 ) 88 96 db s/n (a-weighted) ( note 4 ) 88 96 db inter-channel isolation (f=1khz) ( note 5 ) 90 105 db dc accuracy channel gain mismatch 0.1 0.3 db analog input input voltage (differential input) ( note 6 ) 1.85 2.00 2.15 vp-p input voltage (single-end input) ( note 7 ) 1.85 2.00 2.15 vp-p stereo adc input impedance ( note 8 ) 41 62 k ? note 4. this value is not guaranteed for single-ended inputs. note 5. indicates isolation between l and r when -1dbfs signal is applied. note 6. target input pins are ain1lp, ain1ln, ain1rp, ain1rn. note 7. target input pins are ain2l, ain2r, ain3l, ain3r. note 8. target input pins are ain1lp, ain1ln, ain1rp, ain1rn, ain2l, ain2r, ain3l, ain3r. dac characteristics (ta=25oc; avdd=dvdd=3.3v; bick=64fs; signal freque ncy 1khz; measurement bandwidth=20hz~20khz, fs=48khz, r l =5k ? , c l = 15pf ; ckm mode 0 (ckm[2:0]=000), unless otherwise specified) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) (0dbfs) 80 92 db dynamic range (a-weighted) 90 106 db s/n (a-weighted) 90 106 db inter-channel isolation (f=1khz)( note 9 ) 90 100 db dc accuracy channel gain mismatch 0.2 0.5 db analog output output voltage ( note 10 ) 3.36 3.66 3.96 vp-p load resistance 5 k ? stereo dac load capacitance 30 pf note 9. indicates isolation be tween each dac?s of lch and rch when -1dbfs signal is applied. note 10. full scale output voltage. th e output voltage scales with avdd. analog characteristics
[ak7742] ms1024-e-00_pb 2008/11 - 10 - ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit high level input voltage ( note 11 ) vih 80%dvdd v low level input voltage ( note 11 ) vil 20%dvdd v scl, sda high level input voltage vih 70%dvdd v scl, sda low level input voltage vil 30%dvdd v high level output voltage iout=-100 a voh dvdd-0.5 v low level output voltage iout=100 a ( note 12 ) vol 0.5 v sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 13 ) input leak current (pull-down) ( note 14 ) input leak current xti pin iin iid iix 22 26 10 a a a note 11. except for the scl, sda pin. note 12. except for the sda pin. note 13. except for the test1 pin, xti pin. note 14. the test1 pin has an internal pull-down device, nominally 150k ? . ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v(typ=3.3v, max=3.6v)) parameter min typ max unit power supply current ( note 15 ) normal operation avdd+dvdd 75 122 ma reset (iresetn= ?l? reference data) avdd+dvdd ( note 16 ) 2 ma note 15. depends on the system frequency and contents of dsp program. note 16. this is a reference value when using a crystal oscillator. since most of the supply current at the initial reset state is in the oscillator section, the value may vary according to the crystal type a nd the external circuit. this value is just reference. dc characteristics power consumption
[ak7742] ms1024-e-00_pb 2008/11 - 11 - adc ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) , avdd=dvdd=3.0~3.6v, fs=48khz; note 17 ) parameter symbol min typ max unit pass band (0.005db) ( note 18 ) (-0.02db) (-6.0db) pb 0 21.768 24.00 21.5 khz khz khz stop band sb 26.5 khz pass band ripple ( note 18 ) pr 0.005 db stop band attenuation ( note 19 , note 20 ) sa 80 db group delay distortion ? gd 0 s group delay (ts=1/fs) gd 30 ts digital filter + analog filter characteristics amplitude characteristic 20hz~20.0khz 0.01 db note 17. each parameter is related to the samp ling frequency (fs). hpf response is not included. note 18. pass band is from dc to 21.5khz when fs=48khz. note 19. stop band is from 26.5khz to 3.0455mhz when fs=48khz. note 20. when fs=48khz, the analog modulator samples the analog input at 3.072mhz. therefore the input signal is not attenuated by the digital filter in multiple bands (n x 3.072mhz 21.99khz; n=0, 1, 2, 3 ?) of the sampling frequency. v dac ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) , avdd=dvdd=3.0~3.6v, fs=48khz; note 17 ) parameter symbol min typ max unit digital filter pass band 0.07db ( note 21 ) (-6.0db) pb 0 - 24.0 21.7 - khz khz stop band ( note 21 ) sb 26.2 khz pass band ripple pr 0.01 db stop band attenuation sa 64 db group delay (ts=1/fs) ( note 22 ) gd - 24 ts digital filter + analog filter amplitude characteristic 0~20.0khz 0.5 db note 21. pass band and stop band parameter is relate d to sampling frequency(fs). pb=0.4535fs (at-0.05db), sb=0.5465fs. note 22.the digital filter?s delay is calcu lated as the time from setting 24-bit data into the input register until an analog signal is output. digital filter characteristics
[ak7742] ms1024-e-00_pb 2008/11 - 12 - system clock ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit xti a)with a crystal oscillator frequency(256fs) fs=44.1khz ckm[2:0]= 000 fs=48khz fxti - 11.2896 12.288 - mhz b)with an external clock duty cycle duty 40 50 60 % frequency(256fs) fs=44.1khz ckm[2:0]= 000, 010 fs=48khz fxti 11.0 11.2896 12.288 12.4 mhz frequency (384fs) fs=44.1khz ckm[2:0]= 001 fs=48khz fxti 16.5 16.9344 18.432 18.6 mhz lrck frequency ( note 23 ) fs 7.35 48 96 khz bick frequency a) ckm[2:0]= 001, 010 32 64 fs high level width low level width tbclkh tbclkl 64 64 ns ns frequency fbclk 0.46 3.072 6.144 mhz b) ckm[2:0]= 011 ( note 25 ) 64 fs duty cycle duty 40 50 60 % frequency fbclk 2.75 3.072 3.1 mhz c) ckm[2:0]= 100 ( note 26 ) 32 fs duty cycle duty 40 50 60 % frequency fbclk 230 256 258 khz d) ckm[2:0]= 101 ( note 27 ) 64 fs duty cycle duty 40 50 60 % frequency fbclk 460 512 516 khz note 23. lrck frequency and sampli ng rate (fs) should be the same. note 24. the bick must be divided 32, 48 or 64 clocks correctly. (bick can be selected from 32fs, 48fs or 64fs) note 25. when bick is resource of internal mclk. the bick must be divided 64 clocks correctly. 64fs fixed. note 26. when bick is resource of internal mclk. the bick must be divided 32 clocks correctly. 32fs fixed. note 27. when bick is resource of internal mclk. the bick must be divided 64 clocks correctly. 64fs fixed. switching characteristics
[ak7742] ms1024-e-00_pb 2008/11 - 13 - reset ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit ireset ( note 28 ) trst 600 ns note 28. it is necessity that the power is supplied and master clock is input when the ireset pin goes to ?h?. audio interface 1) sdin1, sdin2, sdou t1, sdout2, sdout3 ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v, cl=20pf) parameter symbol min typ max unit slave mode bick frequency fbclk 32 64 fs bick low level width tbclkl 150 ns bick high level width tbclkh 150 ns delay time from bick ? ? to lrck ( note 29 ) tblrd 40 ns delay time from lrck to bick ? ? ( note 29 ) tlrbd 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns delay time from lrck to serial data output tlrd -10 40 ns delay time from bick ? ? to serial data output ( note 30 ) tbsod -10 40 ns master mode bick frequency fbclk 64 fs bick duty cycle 50 % delay time from bick ? ? to lrck tblrd 40 ns delay time from lrck to bick ? ? tlrbd 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns delay time from bick ? ? to serial data output ( note 30 ) tbsod -30 40 ns note 29. bick rising edge must not occur at the same time as lrck edge. note 30. the serial data output is synchronized to bick falling edge, and held until next bick falling (spec -10ns) in slave mode. in case of the lrck edge comes before bick edge, data will be held until lrck edge (spec -10ns). in master mode, serial data is held until 30ns before falling edge of bick. therefore, please use bick rising edge in both slave and master modes for a safety latch . .
[ak7742] ms1024-e-00_pb 2008/11 - 14 - i 2 cbus interface ( ta=-20 c ~70 c (ak7742eq), ta=-20 c ~85 c (AK7742EN) ; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 31. i 2 c is a registered trademark of philips semiconductors.
[ak7742] ms1024-e-00_pb 2008/11 - 15 - package (ak7742eq) 48pin lqfp (unit: mm) materials and lead specification package: epoxy lead frame: copper lead-finish: soldering (pb free) plate 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 0.10 37 24 25 36 0.09 0.20 1.4 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.3 0.75 0.5
[ak7742] ms1024-e-00_pb 2008/11 - 16 - package (AK7742EN) note: the exposed pad must be open or connected to the ground. materials and lead specification package: epoxy lead frame: copper lead-finish: soldering (pb free) plate 48pin qfn (unit: mm) 6.00 0.05 6.20 0.10 6.00 0.05 0.40 0.18 1 1 0.05 48 12 4-c0.5 48 0.05 0.45 0.10 0.22 0.05 c exposed pad 4.40typ 6.20 0.10 0.85 0.05 c b a 0.05 m 4.40typ 0.02typ 0.005min 0.04max 0.20 0.05 0.45 0.10
[ak7742] ms1024-e-00_pb 2008/11 - 17 - marking (ak7742eq) a km a k7742eq xxxxxxx 1 xxxxxxx: date code iden tifier (7 digits) marking (AK7742EN) xxxxxxx: date code iden tifier (7 digits) 48 1 akm AK7742EN xxxxxxx
[ak7742] ms1024-e-00_pb 2008/11 - 18 - revision history date (yy/mm/dd) revision reason page contents 08/11/07 00 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.
[ak7742] ms1024-e-00_pb 2008/11 - 19 - thank you for your access to akemd product information. more detail product information is available, please contact our sales office or authorized distributors.

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